In an interleaved analog-to-digital converter (ADC), a plurality of converting stages are connected in parallel to an analog input signal. The timing of when the stages are activated is controlled by a clock input to each stage. Typically, the stages are controlled using at least two clock inputs that have different timing. In this manner, the stages are able to process different time slices of the same input signal. The digital outputs of each stage are then combined to form an overall output of the ADC that represents a digital approximation of the input to the ADC. FIG. 1 shows a block diagram of a conventional interleaved ADC. Three stages 100/110/120 are connected in parallel to an input Vin. Each stage forms an interleaved channel. For illustration purposes, only the first two channels and the final (Nth) channel are shown. However, the interleaved ADC may have any number of channels. The first stage 100 may include an ADC 10 (also known as a “flash”) and a multiplying digital-to-analog converter (MDAC) 50. The MDAC 50 includes a digital-to-analog converter (DAC) 20 and an amplifier 30. Vin is input to the ADC 10 to generate a digital input to the DAC 20, which in turn converts the digital output of the ADC 10 back into an analog signal. The analog output of the DAC 20 is then subtracted from Vin and the result input to the amplifier 30 to generate an analog output voltage VO1, which can be used as input to the next stage if the channel is a pipelined channel (not shown). Pipelining, however, is optional and in another embodiment, stage 100 may directly generate a digital output without need for an MDAC, since no other stages would be connected to stage 100. The stages 100/110/120 may include similar components and as with the stage 100, the stages 110 and 120 may also be pipelined. Each stage 100/110/120 is controlled by a respective clock input (Clock1, Clock2 and Clock3) to form an interleaved channel that is operated in parallel with the other channels of the ADC.
The timing configuration of the clock inputs can vary. For instance Clock1 and Clock2 may be phase offset, then the next stage after Stage2 (not shown) may be connected to a clock that is in-phase with Clock1, so that the phases of the clocks alternate in successive fashion. In another embodiment, each of the clocks may operate on different phases. Other configurations are also possible.
Interleaved ADCs are advantageous because by processing different portions of the input in parallel, the effective sampling rate of the ADC is increased without having to apply a faster clock input. However, interleaved ADCs are sensitive to timing issues such as mismatches between the relative timing of the different stages (known as timing or phase mismatch). When stages do not operate at the right times, and in particular when the stages of one channel are time mismatched relative to the stages of another channel, the resulting ADC output will be inaccurate.
Other types of mismatches affecting the accuracy of an interleaved ADC include gain mismatch and bandwidth mismatch, which are related in that bandwidth mismatch produces gain mismatch as well as timing mismatch. Bandwidth mismatch arises due to the fact that each stage is an RC circuit in which the resistive component R corresponds to the resistances of the switches that operate to switch between sample and hold phases of operation, and the capacitive component C corresponds to the sampling capacitors that are used to sample the input applied to the stage. Thus, each stage has an RC time constant that influences the delay that the input experiences as it is processed by the stage and the output of the stage is dependent on this time constant. Bandwidth mismatch occurs when the time constant of an interleaved stage deviates from the time constant of the other interleaved stages, so that the gain experienced by the input in that stage deviates from the other stages' gains. Bandwidth mismatch results in both gain and phase mismatch, because the bandwidth affects both the amplitude and the phase of the sampled signal. The timing of when the signal is sampled or held in that stage may also change as a result of bandwidth mismatch. The extent of the bandwidth mismatch is dependent on the frequency of the input and is generally worse at high frequencies than at low frequencies.